//8192XBR RFE53 version = 35
//VC5337

//TX TSSI

//S0
//autodck dly
//wire [3:0] r_tssi_dck_auto_start_dly = r_page58_14[21:18];
0x5814	0x200EF000
//wire [3:0] r_tssi_adc_sampling_shift_ofdm = r_page58_1C[24:21];
//wire [3:0] r_tssi_adc_sampling_shift_cck = r_page58_1C[28:25];
0x581c	0x3DC80280
//A
0x5824	0x00000843
0x582c	0x00000843
0x5834	0x00000843
0x583c	0x000008E8
0x5844	0x000008E8
0x584c	0x000008E8
0x5854	0x000008C5
0x585c	0x000008C5
//K
0x5828	0x100000C3
0x5830	0x100000C3
0x5838	0x100000C3
0x5840	0x100000C5
0x5848	0x100000C5
0x5850	0x100000C5
0x5858	0x100000C2
0x5860	0x100000C2

//S1
//autodck dly
//wire [3:0] r_tssi_dck_auto_start_dly = r_page78_14[21:18];
0x7814	0x200EF000
//wire [3:0] r_tssi_adc_sampling_shift_ofdm = r_page78_1C[24:21];
//wire [3:0] r_tssi_adc_sampling_shift_cck = r_page78_1C[28:25];
0x781c	0x3DC80280
//A
0x7824	0x0000084B
0x782c	0x0000084B
0x7834	0x0000084B
0x783c	0x000008AC
0x7844	0x000008AC
0x784c	0x000008AC
0x7854	0x000008FD
0x785c	0x000008FD
//K
0x7828	0x100000C2
0x7830	0x100000C2
0x7838	0x100000C2
0x7840	0x100000C6
0x7848	0x100000C6
0x7850	0x100000C6
0x7858	0x100000C0
0x7860	0x100000C0


//tssi tssi_bypass_by_C_max[8:0] = 0x164 (23dBm) 
0x58d8	0x80080164
0x78d8	0x80080164


//edpd
//txagc_bnd settings 
0x81ac	0x3FDA0400 
0x81b0	0x3f914100  
0x82ac	0x3FDA0400 
0x82b0	0x3f914100 
//pwsf
0x81f0	0x0000f060
0x82f0	0x0000f060

//txgapk
//do PSD table
0x8158	0x00001554
0x8170	0x00008000
0x8258	0x00001554
0x8270	0x00008000


///////////////////////////////////////////////////////


// RX LNA gain/bypass mode:14dB/-7dB
// Path A
// 0x4678[15:8]:gain mode
// 0x4678[7:0]:bypass mode
0x4678	0xC7A338E4

// Path B
// 0x475c[15:8]:gain mode  
// 0x475c[7:0]:bypass mode
0x475c	0xCAAC38E4



0xffff 0xffff