MSM USB PHY transceivers

HSUSB PHY

Required properties:
 - compatible: Should be "qcom,usb-hsphy"
 - reg: Address and length of the register set for the device
   Required regs are:
	"core" : the QSCRATCH base register set
 - <supply-name>-supply: phandle to the regulator device tree node
   Required "supply-name" examples are:
	"vdd" : vdd supply for HSPHY digital circuit operation
	"vdda18" : 1.8v supply for HSPHY
	"vdda33" : 3.3v supply for HSPHY
 - qcom,vdd-voltage-level: This property must be a list of three integer
   values (no, min, max) where each value represents either a voltage in
   microvolts or a value corresponding to voltage corner

Optional properties:
 - reg: Additional registers
	"tcsr" : top-level CSR register to be written during power-on reset
		 intialize the internal MUX that controls whether this PHY is
		 used with the USB3 or the USB2 controller.
	"phy_csr" : register region that contains additional PHY CSRs that
		    offer additional control apart from the QSCRATCH registers.
		    These handle functions such as controlling the internal
		    reference clock buffer and powering on/off the entire PHY.

 - qcom,hsphy-init: Init value used to override HSPHY parameters into
   QSCRATCH register. This 32-bit value represents parameters as follows:
		bits 0-5   PARAMETER_OVERRIDE_A
		bits 6-12  PARAMETER_OVERRIDE_B
		bits 13-19 PARAMETER_OVERRIDE_C
		bits 20-25 PARAMETER_OVERRIDE_D
 - qcom,ext-vbus-id: If present, indicates that the PHY does not handle VBUS and ID changes.
 - qcom,vbus-valid-override: If present, indicates VBUS pin is not connected to
   the USB PHY and the controller must rely on external VBUS notification in
   order to manually enable the D+ pull-up resistor.
 - qcom,primary-phy: If present, indicates this is a secondary PHY and is
   dependent on the primary PHY referenced by this phandle.
 - qcom,set-pllbtune: If present, PLL tune is required in PHY initialization.
 - qcom,num_ports: Indicates the number of ports that supported by the HS PHY.
   If omitted, defaults to 1
 - qcom,sleep-clk-reset: If present, the HSUSB PHY sleep clock supports the clk_reset
   operation, and should be called during initialization.
 - qcom,vdda-force-on: If present, HW requires a workaround that forces 1.8V and 3.1V
		       regulator supplies to be left on even when PHY enters into
		       low power mode.

Example:
	hsphy@f9200000 {
		compatible = "qcom,usb-hsphy";
		reg = <0xf9200000 0xfc000>;
		qcom,hsphy-init = <0x00D191A4>;
		vdd-supply = <&pm8841_s2_corner>;
		vdda18-supply = <&pm8941_l6>;
		vdda33-supply = <&pm8941_l24>;
		qcom,num_of_ports = <3>;
		qcom,vdd-voltage-level = <1 5 7>;
	};

SSUSB PHY

Required properties:
 - compatible: Should be "qcom,usb-ssphy"
 - reg: Address and length of the register set for the device
 - <supply-name>-supply: phandle to the regulator device tree node
   Required "supply-name" examples are:
	"vdd" : vdd supply for SSPHY digital circuit operation
	"vdda18" : 1.8v high-voltage analog supply for SSPHY
 - qcom,vdd-voltage-level: This property must be a list of three integer
   values (no, min, max) where each value represents either a voltage in
   microvolts or a value corresponding to voltage corner

Optional properties:
 - qcom,vbus-valid-override: If present, indicates VBUS pin is not connected to
   the USB PHY and the controller must rely on external VBUS notification in
   order to manually relay the notification to the SSPHY.
 - qcom,deemphasis-value: This property if present represents ss phy
   deemphasis value to be used for overriding into SSPHY register.
 - qcom,primary-phy: If present, indicates this is a secondary PHY and is
   dependent on the primary PHY referenced by this phandle.
 - qcom,override-pll-calibration: If present, program PHY register to overrride
	the automatic PHY PLL calibration settings.
 - qcom,qmp-misc-config: If present, program PHY miscellaneous device-specific
	registers.

Example:
	ssphy@f9200000 {
		compatible = "qcom,usb-ssphy";
		reg = <0xf9200000 0xfc000>;
		vdd-supply = <&pm8841_s2_corner>;
		vdda18-supply = <&pm8941_l6>;
		qcom,vdd-voltage-level = <1 5 7>;
		qcom,deemphasis-value = <26>;
	};

SSUSB-QMP PHY

Required properties:
 - compatible: Should be "qcom,usb-ssphy-qmp"
 - reg: Address and length of the register set for the device
   Required regs are:
   "qmp_phy_base" : QMP PHY Base register set.
 - <supply-name>-supply: phandle to the regulator device tree node
   Required "supply-name" examples are:
	"vdd" : vdd supply for SSPHY digital circuit operation
	"vdda18" : 1.8v high-voltage analog supply for SSPHY
 - qcom,vdd-voltage-level: This property must be a list of three integer
   values (no, min, max) where each value represents either a voltage in
   microvolts or a value corresponding to voltage corner

Optional properties:
- reg: Address and length of the register set for the device
  "qmp_ahb2phy_base" : SS AHB2PHY CSR register set.
- "vls_clamp_reg" : top-level CSR register to be written to enable phy vls
   clamp which allows phy to detect autonomous mode.
- qcom,vbus-valid-override: If present, indicates VBUS pin is not connected to
   the USB PHY and the controller must rely on external VBUS notification in
   order to manually relay the notification to the SSPHY.
- qcom,emulation: Indicates that we are running on emulation platform.

Example:
	ssphy0: ssphy@f9b38000 {
		compatible = "qcom,usb-ssphy-qmp";
		reg = <0xf9b38000 0x16c>,
			<0xf9b3e000 0x3ff>,
			<0x01947244 0x4>;
		reg-names = "qmp_phy_base",
			"qmp_ahb2phy_base",
			"vls_clamp_reg";
		vdd-supply = <&pmd9635_l4>;
		vdda18-supply = <&pmd9635_l8>;
		qcom,vdd-voltage-level = <0 900000 1050000>;
		qcom,vbus-valid-override;
	};

QUSB2 High-Speed PHY

Required properties:
 - compatible: Should be "qcom,qusb2phy"
 - reg: Address and length of the QUSB2 PHY register set
 - reg-names: Should be "qusb_phy_base".
 - <supply-name>-supply: phandle to the regulator device tree node
   Required supplies are:
	"vdd" : vdd supply for digital circuit operation
	"vdda18" : 1.8v high-voltage analog supply
	"vdda33" : 3.3v high-voltage analog supply
 - qcom,vdd-voltage-level: This property must be a list of three integer
   values (no, min, max) where each value represents either a voltage in
   microvolts or a value corresponding to voltage corner
 - clocks: a list of phandles to the PHY clocks. Use as per
   Documentation/devicetree/bindings/clock/clock-bindings.txt
 - clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
   property. Required clocks are "cfg_ahb_clk" and "phy_reset".
 - phy_type: Should be one of "ulpi" or "utmi". ChipIdea core uses "ulpi" mode.

Optional properties:
 - reg: Address and length register set to control QUSB2 PHY
   "qscratch_base" : QSCRATCH base register set.
   "tune2_efuse_addr": EFUSE based register address to read TUNE2 parameter.
   via the QSCRATCH interface.
   "emu_phy_base" : phy base address used for programming emulation target phy.
   "ref_clk_addr" : ref_clk bcr address used for on/off ref_clk before reset.
   "tcsr_phy_clk_scheme_sel": address used to determine QUSB PHY clk source.
 - reg-names: Should be "qscratch_base". The qscratch register bank
   allows us to manipulate QUSB PHY bits eg. to enable D+ pull-up using s/w
   control in device mode. The reg-names property is required if the
   reg property is specified.
 - qcom,qusb-phy-init-seq: QUSB PHY initialization sequence with value,reg pair.
 - qcom,emu-init-seq : emulation initialization sequence with value,reg pair.
 - qcom,phy-pll-reset-seq : emulation PLL reset sequence with value,reg pair.
 - qcom,emu-dcm-reset-seq : emulation DCM reset sequence with value,reg pair.
 - qcom,tune2-efuse-bit-pos: TUNE2 parameter related start bit position with EFUSE register
 - qcom,tune2-efuse-num-bits: Number of bits based value to use for TUNE2 high nibble
 - qcom,emulation: Indicates that we are running on emulation platform.
 - qcom,hold-reset: Indicates that hold QUSB PHY into reset state.
 - qcom,enable-dpdm-pulsing: enables dp and dm pulsing for PMIC driver to
   perform charger detection.
 - qcom,tune2-efuse-correction: The value to be adjusted from the higher nibble of TUNE2
   for improved rise/fall times.

Example:
	qusb_phy: qusb@f9b39000 {
		compatible = "qcom,qusb2phy";
		reg = <0x00079000 0x7000>,
			<0x08af8800 0x400>;
		reg-names = "qusb_phy_base",
			    "qscratch_base";
		vdd-supply = <&pm8994_s2_corner>;
		vdda18-supply = <&pm8994_l6>;
		vdda33-supply = <&pm8994_l24>;
		qcom,vdd-voltage-level = <1 5 7>;
		qcom,tune2-efuse-bit-pos = <21>;
		qcom,tune2-efuse-num-bits = <3>;

		clocks = <&clock_rpm clk_ln_bb_clk>,
				 <&clock_gcc clk_gcc_rx2_usb1_clkref_clk>,
				 <&clock_gcc clk_gcc_usb_phy_cfg_ahb2phy_clk>,
				 <&clock_gcc clk_gcc_qusb2_phy_reset>;
		clock-names = "ref_clk_src", "ref_clk", "cfg_ahb_clk", "phy_reset";
	};

SSUSB-PP Super-Speed PHY

Required properties:
 - compatible: Should be "qcom,usb-ssphy-pp"
 - reg: Address and length of the register set for the device
   Required regs are:
   "ssphy_phy_base" : SSUSB-PP PHY Base register set.
   "qscratch_phy"   : SSUSB-PP PHY QSCRATCH register set.
 - <supply-name>-supply: phandle to the regulator device tree node
   Required "supply-name" examples are:
	"vdd" : vdd supply for SSPHY digital circuit operation
	"vdda18" : 1.8v high-voltage analog supply for SSPHY
 - qcom,vdd-voltage-level: This property must be a list of three integer
   values (no, min, max) where each value represents either a voltage in
   microvolts or a value corresponding to voltage corner
 - clocks: a list of phandles to the PHY clocks. Use as per
   Documentation/devicetree/bindings/clock/clock-bindings.txt
 - clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
   property. Required clocks are "phy_phy_reset" and "phy_reset".

Example:
	ssphy: ssphy@f92f8800   {
		compatible = "qcom,usb-ssphy-pp";
		reg = <0xfca01000 0xAC>,
		<0xf92f8800 0x3ff>;
		reg-names = "ssphy_base",
			    "qscratch_phy";
		vdd-supply = <&stub_regulator_vdd_mx>;
		vdda18-supply =  <&stub_regulator_1p8v>;
		qcom,vdd-voltage-level = <1 5 7>;
		qcom,ext-vbus-id;
		clocks = <&clock_gcc clk_gcc_usb3_phy_reset>,,
			 <&clock_gcc clk_gcc_usb3phy_phy_reset>;
		clock-names = "phy_reset", "phy_phy_reset";
		status = "disable";
	};

HSUSB-PP High-Speed PHY

Required properties:
 - compatible: Should be "qcom,usb-hsphy-pp"
 - reg: Address and length of the HSUSB-PP PHY register set
   Required regs are:
   "hsphy_phy_base" : HSUSB-PP PHY Base register set.
   "qscratch_phy"   : HSUSB-PP PHY QSCRATCH register set.
 - <supply-name>-supply: phandle to the regulator device tree node
   Required supplies are:
	"vdd" : vdd supply for digital circuit operation
	"vdda18" : 1.8v high-voltage analog supply
	"vdda33" : 3.3v high-voltage analog supply
 - qcom,vdd-voltage-level: This property must be a list of three integer
   values (no, min, max) where each value represents either a voltage in
   microvolts or a value corresponding to voltage corner

Optional properties:
- qcom,vbus-valid-override: If present, indicates VBUS pin is not connected to
   the USB PHY and the controller must rely on external VBUS notification in
   order to manually relay the notification to the SSPHY.
- qcom,vdda-force-on: If present, HW requires a workaround that forces 1.8V and 3.1V
  regulator supplies to be left on even when PHY enters into
  low power mode.

Example:
	hsphy: hsphy@f92f8800 {
		compatible = "qcom,usb-hsphy-pp";
		reg = <0xfca00000 0x200>,
			<0xf92f8800 0x3ff>;
		reg-names = "hsphy_base",
			     "qscratch_phy";
		qcom,hsphy-init = <0x031188C4>;
		vdd-supply = <&stub_regulator_vdd_mx>;
		vdda18-supply = <&stub_regulator_1p8v>;
		vdda33-supply = <&stub_regulator_3p3v>;
		qcom,vdd-voltage-level = <1 5 7>;
		qcom,ext-vbus-id;
		qcom,vbus-valid-override;
		qcom,vdda-force-on;
		status = "disable";
	};
