//=======================	
// PAGE_8 ( FPGA_PHY0 )  	
//=======================	
0x800	0x80040000
0x804	0x00000003
0x808	0x0000fc00
0x80c	0x0000000A
0x810	0x10001331
0x814	0x020c3d10
0x818	0x02200385  // [30:29] is DTR Set off now. turn off RIFS: 0x00200185 turn on RIFS: 0x00200385
0x81c	0x00000000
0x820	0x01000100 // 0x01000000 (SI); 0x01000100 (PI)
0x824	0x00390204 //88E: 0x824[9]=1b1
0x828	0x00000000
0x82c	0x00000000
0x830	0x00000000
0x834	0x00000000
0x838	0x00000000
0x83c	0x00000000
0x840	0x00010000 //RF to standby mode
0x844	0x00000000
0x848	0x00000000
0x84c	0x00000000
0x850	0x00000000 // RF wakeup; TBD
0x854	0x00000000 // RF sleep; TBD 
0x858	0x569a11a9
0x85c	0x01000014 // AFE ctrl reg (ASIC)  RX AD3 CCA mode 
0x860	0x66f60110
0x864	0x061f0649
0x868	0x00000000
0x86c	0x27272700 //Path-A 11M/5.5M/2M TX AGC codeword               
if((ODM_BOARD_TYPE &(ODM_BOARD_EXT_PA|ODM_BOARD_EXT_LNA)))
{
	0x870	0x07000300
}
else
{
	0x870	0x07000760 // z2: 0x03000300; 92C RF: 0x07000700 (2 internal PA); 92S RF: 0x03000700 (one internal PA)
}
0x874	0x25004000 // 0x874[27:24]=4b0101 ADC Gain x 1
0x878	0x00000808 //RF mode for standby & rx_low_power codeword
0x87c	0x00000000  // TST mode
0x880	0xb0000c1c // AFE ctrl reg (ASIC); 0x880[17]=1b0
0x884	0x00000001 // AFE ctrl reg (ASIC); 0x884[2:1]=0
0x888	0x00000000 // AFE ctrl reg (ASIC)
0x88c	0xccc000c0 // [10:1] is r_rdy_cnt for sleep/standby mode; [27]&[31] are MCS_IND
0x890	0x00000800
0x894	0xfffffffe
0x898	0x40302010
0x89c	0x00706050
//	
//=======================	
// PAGE_9 ( FPGA_PHY1 )  	
//=======================	
0x900	0x00000000
0x904	0x00000023
0x908	0x00000000
0x90c	0x81121111 // tx antenna by contorl register
0x910	0x00000002 // 88E:RX_Status; Reg910[15:0]=16d2 
0x914	0x00000201 // 88E:Antenna Diversity
//                       	
//=======================	
// PAGE_A ( CCK_PHY0 )   	
//=======================	
0xa00	0x00d047c8
0xa04	0x80ff000c
0xa08	0x8c838300 // MP: 0x88838300; driver: 0x8ccd8300 
0xa0c	0x2e7f120f
0xa10	0x9500bb78
0xa14	0x1114D028
0xa18	0x00881117
0xa1c	0x89140f00
if((ODM_BOARD_TYPE &(ODM_BOARD_EXT_PA|ODM_BOARD_EXT_LNA)))
{
	0xa20	0x13130000
	0xa24	0x060a0d10
	0xa28	0x00000103
}
else
{
	0xa20	0x1a1b0000
	0xa24	0x090e1317
	0xa28	0x00000204
}
0xa2c	0x00d30000
0xa70	0x101fbf00
0xa74	0x00000007
0xa78	0x00000900
0xa7c	0x225b0606
0xa80	0x218075b1 //88E: CCK LNA 2 to 3 bit mapping:0xa80[23]=1b1 0xa80[7]=1b1 CCK agc_rpt as new format
//0xa80	0x21003210
//   	
//=======================	
// PAGE_B                	
//=======================	
if((ODM_BOARD_TYPE &(ODM_BOARD_EXT_PA|ODM_BOARD_EXT_LNA)))
{
	0xb2c	0x00000000
}
else
{
	0xb2c	0x80000000 //default LNA
}
//                       	
//=======================	
// PAGE_C ( OFDM_PHY0 )  	
//=======================	
0xc00	0x48071d40
0xc04	0x03a05611
0xc08	0x000000e4 // [8:4] is about DBG_GPIO selection
0xc0c	0x6c6c6c6c
0xc10	0x08800000
0xc14	0x40000100
0xc18	0x08800000
0xc1c	0x40000100
0xc20	0x00000000 // DTR TH
0xc24	0x00000000 // DTR TH
0xc28	0x00000000 // DTR TH
0xc2c	0x00000000 // DTR TH
0xc30	0x69e9ac47 // PWED_TH option2
0xc34	0x469652af
0xc38	0x49795994
0xc3c	0x0a97971c
0xc40	0x1f7c403f
0xc44	0x000100b7
0xc48	0xec020107 //[1]=1:enable L1_SBD
0xc4c	0x007f037f // turn off edcca
0xc50	0x69553420
0xc54	0x43bc0094
0xc58	0x00013169 // simple agc settling time
0xc5c	0x00250492 // switch RXHP corner
0xc60	0x00000000 // DTR TH
0xc64	0x7112848b //L1-SBD  //31168a8b for 6M sen. 0x5116828b 0x5116848b //by Gary
0xc68	0x47c00bff //L1-SBD  
0xc6c	0x00000036 //L1-SBD
0xc70	0x2c7f000d // disable AGC flow-1 
0xc74	0x020610db // 1st and 2nd BB PW time
0xc78	0x0000001f
0xc7c	0x00b91612
if((ODM_BOARD_TYPE &(ODM_BOARD_EXT_PA|ODM_BOARD_EXT_LNA)))
{
	0xc80	0x2d4000b5
}
else
{
	0xc80	0x390000e4 //-1dB  
}
0xc84	0x21f60000
0xc88	0x40000100
0xc8c	0x20200000
0xc90	0x00091521 // TX Power Training for path-A
0xc94	0x00000000
0xc98	0x00121820 // TX Power Training for path-B
0xc9c	0x00007f7f // turn off pre-cca  
0xca0	0x00000000
0xca4	0x000300A0
0xca8	0x00000000 // reserved
0xcac	0x00000000 // reserved
0xcb0	0x00000000 // reserved
0xcb4	0x00000000 // reserved
0xcb8	0x00000000 // reserved
0xcbc	0x28000000
0xcc0	0x00000000 // reserved
0xcc4	0x00000000 // reserved
0xcc8	0x00000000 // reserved
0xccc	0x00000000 // reserved
0xcd0	0x00000000 // reserved
0xcd4	0x00000000 // reserved
0xcd8	0x64b22427 // reserved
0xcdc	0x00766932 // reserved
0xce0	0x00222222
0xce4	0x00000000
0xce8	0x37644302
0xcec	0x2f97d40c
//                       	
//=======================	
// PAGE_D ( OFDM_PHY1 )  	
//=======================	
0xd00	0x00000740 //88E: support<mcs8
0xd04	0x00020401
0xd08	0x0000907f
0xd0c	0x20010201
0xd10	0xa0633333
0xd14	0x3333bc43
0xd18	0x7a8f5b6f
0xd2c	0xcc979975
0xd30	0x00000000
0xd34	0x80608000
0xd38	0x00000000
0xd3c	0x00127353
0xd40	0x00000000
0xd44	0x00000000
0xd48	0x00000000
0xd4c	0x00000000
0xd50	0x6437140a
0xd54	0x00000000
0xd58	0x00000282
0xd5c	0x30032064
0xd60	0x4653de68
0xd64	0x04518a3c //[26]=1:enable L1-SBD
0xd68	0x00002101
0xd6c	0x2a201c16 // DTR
0xd70	0x1812362e // DTR 
0xd74	0x322c2220 // DTR 
0xd78	0x000e3c24 // DTR 
//=======================	
// PAGE_E                	
//=======================	
0xe00	0x2d2d2d2d // Path-A TX AGC codewod; 6M. 9M. 12M. 18M          
0xe04	0x2d2d2d2d // Path-A TX AGC codewod; 24M. 36M. 48M. 54M
0xe08	0x0390272d // Path-A TX AGC codewod; MCS32. 1M            
0xe10	0x2d2d2d2d // Path-A TX AGC codewod; MCS0. MCS1. MCS2. MCS3    
0xe14	0x2d2d2d2d // Path-A TX AGC codewod; MCS4. MCS5. MCS6. MCS7    
0xe18	0x2d2d2d2d // Path-A TX AGC codewod; MCS8. MCS9. MCS10. MCS11  
0xe1c	0x2d2d2d2d // Path-A TX AGC codewod; MCS12. MCS13. MCS14. MCS15
0xe28	0x00000000
0xe30	0x1000dc1f // 0xe30~0xe60: IQK   
0xe34	0x10008c1f
0xe38	0x02140102
0xe3C	0x681604c2
0xe40	0x01007c00
0xe44	0x01004800
0xe48	0xfb000000
0xe4c	0x000028d1
0xe50	0x1000dc1f
0xe54	0x10008c1f
0xe58	0x02140102
0xe5C	0x28160d05
0xe60	0x00000008
//0xe64	0x281600a0 // Reserved in 92C/88C
0xe68	0x001b25a4
0xe6c	0x00c00014 // AFE ctrl reg (ASIC)  Blue-Tooth  
0xe70	0x00c00014 // AFE ctrl reg (ASIC)  RX_WAIT_CCA 
0xe74	0x01000014 // AFE ctrl reg (ASIC)  TX_CCK_RFON 
0xe78	0x01000014 // AFE ctrl reg (ASIC)  TX_CCK_BBON 
0xe7c	0x01000014 // AFE ctrl reg (ASIC)  TX_OFDM_RFON
0xe80	0x01000014 // AFE ctrl reg (ASIC)  TX_OFDM_BBON
0xe84	0x00c00014 // AFE ctrl reg (ASIC)  TX_TO_RX    
0xe88	0x01000014 // AFE ctrl reg (ASIC)  TX_TO_TX    
0xe8c	0x00c00014 // AFE ctrl reg (ASIC)  RX_CCK      
0xed0	0x00c00014 // AFE ctrl reg (ASIC)  RX_OFDM     
0xed4	0x00c00014 // AFE ctrl reg (ASIC)  RX_WAIT_RIFS
0xed8	0x00c00014 // AFE ctrl reg (ASIC)  RX_TO_RX    
0xedc	0x00000014 // AFE ctrl reg (ASIC)  Standby     
0xee0	0x00000014 // AFE ctrl reg (ASIC)  Sleep       
if((ODM_BOARD_TYPE &(ODM_BOARD_EXT_PA|ODM_BOARD_EXT_LNA)))
{
	0xee8	0x32555448
}
else
{
	0xee8	0x21555448
}
0xeec	0x01c00014 // AFE ctrl reg (ASIC)  PMPD_ANAEN  
//=======================	
// PAGE_F              	
//=======================	
0xf14	0x00000003 // debug port selection. 0x0~0x3: PHY DBG 0x4~0x5: MAC DBG
0xf4c	0x00000000 // Only for FPGA PMAC 
0xf00	0x00000300 // enable BBRSTB bcz HSSI use clk_bb
0xffff 0xffff